library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity ROM is
generic (	N_DATA	: natural := 32;
		N_ROWS	: natural := 48;
		N_COLS	: natural := 8 );
port( 	rst			: in   std_logic;
		address		: in   STD_LOGIC_VECTOR (N_DATA-1 downto 0);
		vliw_en		: in   std_logic;
		Instruction	: out STD_LOGIC_VECTOR (N_DATA*2-1 downto 0)
);
end ROM;

architecture Behav32 of ROM is
type Rom_Array is array (0 to N_ROWS-1) of std_logic_vector(N_COLS-1 downto 0);
signal content : Rom_Array;

begin

FILL_IN_MEM: process (address,vliw_en)
	variable index : integer := 0;
	begin		
		Content <= (	X"20", X"45", X"00", X"0d",
					X"24", X"47", X"00", X"0f", 
					X"00", X"e5", X"58", X"22",
					X"ac", X"0b", X"00", X"0a",
					X"00", X"a7", X"70", X"21",
					X"51", X"61", X"00", X"01",
					X"0c", X"00", X"00", X"04",
					X"54", X"00", X"00", X"00",
					X"54", X"00", X"00", X"00",
					X"8c", X"02", X"00", X"0a",
					X"01", X"67", X"70", X"21",
					X"00", X"42", X"b0", X"24",
					X"01", X"c1", X"a0", X"2d",
					X"17", X"e0", X"ff", X"c4",
					X"54", X"00", X"00", X"00",
					X"54", X"00", X"00", X"00",
					X"54", X"00", X"00", X"00",
					X"54", X"00", X"00", X"00"
					);

		index := to_integer(unsigned(address));
		if vliw_en = '0' then
			Instruction(N_DATA*2-1 downto N_DATA) <= (others => '0');
			Instruction(N_DATA-1 downto 0) <= content(index) & content(index+1) & content(index+2) & content(index+3);
		else --vliw_en = '1'
			Instruction <= content(index+4) & content(index+5) & content(index+6) & content(index+7)
						& content(index) & content(index+1) & content(index+2) & content(index+3)
					      ;
		end if;
	end process;

end Behav32;
--		Content <= (	"00100000","01000101","00000000","00001101", --addi r5,r2,#13
--					"00100000","01000101","00000000","00001111", --addi r5,r2,#15
--					"10101100","00000001","00000000","00001010", --sw 10(r0),r1
--					"01010000","00101011","00000000","00000001", --slli r11,r1,#1
--					"00001100","00000000","00000000","00001000", --jal #28 
--					"01010100","00000000","00000000","00000000", --nop
--					"01010100","00000000","00000000","00000000", --nop
--					"00000001","01100001","01110000","00100010", --sub r14,r11,r1
--					"10001100","00000001","00000000","00001010", --lw r1,10(r0)
--					"00000001","11000001","10100000","00101101", --sge r20,r14,r1
--					"00010111","11100000","00000000","00101000", --bnez r31, #38
--					"00000000","00100001","00001000","00100110"  --xor r1,r1,r1
--			);

--		Content <= (	"00100000","01000101","00000000","00001101", --addi r5,r2,#13
--					"00100100","01000110","00000000","00001110", --addui r6,r2,#14
--					"00100000","01000111","00000000","00001111", --addi r7,r2,#15
--					"00100100","01000100","00000000","00001100", --addui r4,r2,#12
--					"00100000","01000011","00000000","00001011", --addi r3,r2,#11
--					"00000000","11100101","01110000","00100010", --sub r14,r7,r5
--					"10101100","00000110","00000000","00001010", --sw 10(r0),r6
--					"01010000","00101011","00000000","00000001", --slli r11,r1,#1
--					"00000000","11000101","00001000","00100110", --xor r1,r5,r1
--					"00001100","00000000","00000000","00001000", --jal #28 
--					"01010100","00000000","00000000","00000000", --nop
--					"01010100","00000000","00000000","00000000" --nop
--			);